Characterization of Interface and Bulk Traps in Ultrathin Atomic Layer-Deposited Oxide Semiconductor MOS Capacitors With HfO2/In2O3 Gate Stack by C-V and Conductance Method

Oxide semiconductors have attracted revived interest for complementary metal–oxide–semiconductor (CMOS) back-end-of-line (BEOL) compatible devices monolithic 3-dimensional (3D) integration. To obtain a high-quality oxide/semiconductor interface and bulk semiconductor, it is critical to enhance the performance of oxide semiconductor transistors. Atomic layer-deposited (ALD) indium (In 2 O 3 ) has been reported with superior such as high drive current, mobility, steep subthreshold slope, ultrathin channel. In this work, traps in MOS gate stack ALD transistors are systematically studied by using C–V conductance method. A low EOT 0.93 nm achieved directly from accumulation capacitance measurement, indicating interface. Defects energy levels subgap confirmed be responsible peak G P /ω versus ω curves TCAD simulation G–V characteristics. n-type doping 1×10 20 /cm extracted measurement. density states (DOS) 3.3×10 cm −3 eV −1 method, which contributes electron density. The further confirms capability channel thickness scaling because charge neutrality level aligns deeply inside conduction band.